`include "defines.v"
module id_ex(
    input clk,
    input rst,
    // from id 
    input wire[`InstBus] Inst_i,
    input wire[`InstAddrBus] InstAddr_i,
    input wire[`RegBus] rdata1_i,
    input wire[`RegBus] rdata2_i,
    input wire[`RegBus] rdata_csr_i,
    
    //from ctrl
    input wire[`Hold_Flag_Bus] hold_flag_i,//to stop the assembly line
    
    //to ex
    output reg[`InstBus] Inst_o,
    output reg[`InstAddrBus] InstAddr_o,
    output reg[`RegBus] rdata1_o,
    output reg[`RegBus] rdata2_o,
    output reg[`RegBus] rdata_csr_o

    
);

always @(posedge clk)
    begin
        if (rst == `RstEnable)
            begin
                Inst_o <= `ZeroWord;
                InstAddr_o <= `ZeroWord;
                rdata1_o <= `ZeroWord;
                rdata2_o <= `ZeroWord;
                rdata_csr_o <= `ZeroWord;
            end
        else if (hold_flag_i >= `Hold_Id)
            begin
                Inst_o <= `INST_NOP;
                InstAddr_o <= InstAddr_i;
                rdata1_o <= `ZeroWord;
                rdata2_o <= `ZeroWord;
                rdata_csr_o <= `ZeroWord;
            end
        else
            begin
                Inst_o <= Inst_i;
                InstAddr_o <= InstAddr_i;
                rdata1_o <= rdata1_i;
                rdata2_o <= rdata2_i;
                rdata_csr_o <= rdata_csr_i;
            end
    end



endmodule